The present invention relates generally to a semiconductor chip and a wire bonding method for a semiconductor chip. More particularly, the present invention relates to a semiconductor chip comprising a bonding window that is formed on a bonding pad and has a smaller size than that of a wire ball. This can prevent the bonding pad from being degraded by corrosion during reliability tests and during a manufacturing process of the chip. The present invention also relates to a wire bonding method for making the semiconductor chip described above.
The wire bonding process is one method for connecting a semiconductor chip to inner leads of the lead frame or to wirings of a circuit board. Bonding pads of the semiconductor chip are connected to the lead frame or to the circuit board by gold or aluminum wires having a diameter of about 0.8-1.5 .mu.m.
The conditions of the bonding process and the equipment required for such a process vary depending on the wire material used. When using a gold wire or an aluminum wire, however, the wire is generally supplied to a bonding head by a wire spool and the bonding of the wire is performed by this bonding head. When the bonding head is aligned above the bonding pad of the semiconductor chip, the wire is attached onto the bonding pad by one of: a thermo-compression bonding method carried out under high temperature and high pressure; an ultrasonic bonding method applying a vibration under high pressure; or a thermosonic bonding method applying a vibration under high temperature and high pressure.
In a wire bonding method using a gold wire, the wire is attached by the ball bonding process using a bonding head which comprises a capillary having a fine passage. The wire is supplied through the passage of the capillary and forms a ball by having a high voltage applied to its end. The ball of melted wire is then pressed onto the bonding pad to attach the wire to the bonding pad.
FIG. 1 is a schematic sectional view showing a bonding of a wire on a bonding pad of a semiconductor chip by ball bonding process using a gold wire. Initially, certain circuit elements (not shown) are formed on the semiconductor substrate 1. This substrate generally comprises silicon. A surface-smoothing layer 2 such as boron phosphorous silica glass (BPSG) is then formed over the substrate 1. Next, a bonding pad 3 for the semiconductor chip is formed on the surface-smoothing layer 2 by depositing a metal such as aluminum over the smoothing layer 2. The circuit elements on the semiconductor substrate 1 are connected to external equipment through the bonding pad 3. After forming the bonding pad 3, the whole surface of the semiconductor chip is covered with passivation layer 4 such as silicon nitride (Si.sub.3 N.sub.4). Then, a bonding window with a width of W.sub.1 is formed in the passivation layer 4. The chip is then subjected to a high temperature to cause the formation of an oxide layer 5 over the bonding pad 3. This oxide layer 5 results from the reaction of the metal in the bonding pad 3 with air at a high temperature. The wire ball 6 formed at the end of the wire 7 is then pressed by the capillary 8 onto the bonding pad 3 through the bonding window.
The conventional wire bonding method has some drawbacks, however. First, since the bonding window is larger than the wire ball 6, the capillary 8 may impact on the bonding pad 3 during a ball bonding process while pressing the wire ball 6. This impact can break the oxide layer 5 covering the bonding pad 3, thus exposing the surface of the bonding pad 3 not covered with the wire ball, which can cause the surface to become corroded.
In particular, after the completion of packaging, the bonding pad in the conventional device tends to be corroded and degraded during standard reliability tests such as PCT (Pressure Cooker Test) or T/C (Temperature Cycling). This is especially true with the PCT, which generally takes place in a pressure cooker at 100% humidity and at a temperature of about 121.degree. C. A more detailed description of PCT and T/C can be found in MIL standard MIL-STD-883D, test method 1010.7, JEDEC standard No. 22-B, test method A102-A, and JEDEC standard No. 22-B, test method A104, all of which are herein incorporated by reference.
Second, although it is desirable to reduce the designed chip in order to reduce the size of the whole semiconductor device, this conventional method has a limitation in reducing the size of the semiconductor device since the conventional wire bonding process can be performed only under the condition that the bonding window has 90.times.90 .mu.m.sup.2 or more of dimension.